Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow are highly dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Software and hardware “tools” then verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to all design flows. First, the specifications for the new microcircuit are described in terms of logical operations, typically using a hardware design language (HDL), such as VHDL. After the accuracy of the logical design is confirmed, the logical design is converted into device design data by synthesis software. The device design data, in the form of a schematic, represents the specific electronic devices, such as transistors, resistors, and capacitors, which will achieve the desired logical result and their interconnections. Preliminary timing estimates for portions of the circuit may also be made at this stage, using an assumed characteristic speed for each device. This schematic generally corresponds to the level of representation displayed in conventional circuit diagrams.
Once the relationships between circuit devices have been established, the design is again transformed into physical design data describing specific geometric elements. These geometric elements, often referred to as a “layout” design, define the shapes that will be created in various materials to form the specified circuit devices. Custom layout editors, such as Mentor Graphics' IC Station or Cadence's Virtuoso are commonly used for this task. Automated place and route tools also will frequently be used to define the physical layouts, especially of wires that will be used to interconnect the circuit devices. Each layer of the microcircuit will have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device. For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices. Thus, the layout design data represents the patterns that will be written onto masks to fabricate the desired microcircuit using, for example, photolithographic processes.
Modern integrated circuits typically will be formed of multiple layers of material, such as metal, diffusion material, and polysilicon. During the manufacturing process, layers of material are formed on top of one another sequentially. After each layer is created, portions of the layer are removed to form structures. Together, the structures of material form the functional circuit devices, such as transistors, capacitors and resistors, which will make up the integrated circuit. Before a new layer is formed over the structures in an existing layer, however, the existing layer must be polished to ensure planarity. Polishing using any of various types of polishing processes sometimes will generically be referred to as “planarization.”
One problem with conventional planarization methods is that different materials will have different densities, so softer materials will be polished more than harder materials. As a result, a layer's surface may become uneven, causing the next layer to be more uneven. In some situations, the uppermost layers of material may have a very irregular surface topography. Such irregular surface topographies may cause a variety of flaws in the circuit structures, such as holes, loss of contact, and other manufacturing defects.
To improve the planarity of a layer of material, the integrated circuit designer (or manufacturer) often will analyze a circuit layout design for empty regions in the layer. That is, the designer or manufacturer will review the density of the geometric elements representing the structures that will be formed in the layer (sometimes referred to as “pattern density”), to identify regions that are empty of these geometric elements. The designer or manufacturer will then modify the circuit layout design to fill these empty regions with data representing “dummy” or “fill” geometric elements. That is, the designer or manufacturer will increase the density of the geometric elements in the circuit layout design for the layer by adding geometric elements that will form non-functional structures. When the circuit is manufactured, these “fill” structures will be formed alongside the “functional” structures (i.e., the structures used to form functional circuit devices), so that the overall surface of the layer is relatively flat. This type of corrective technique will often be implemented using a software application for identifying and manipulating structures defined in a circuit layout design, such as the CALIBRE® verification and manufacturability software tools available from Mentor Graphics® Corporation of Wilsonville, Oreg.
While this corrective technique usually improves the planarity of layers in an integrated circuit, its implementation is often unpredictable. Many conventional fill addition processes add fill geometric elements to the integrated circuit design in order to bring the overall geometric element density up to a target value. While increasing the pattern density in a layer of the design typically will increase the corresponding thickness of the material in the manufactured integrated circuit, the amount of the increase can be very unpredictable. In addition to being dependent upon the density of the geometric elements in the integrated circuit design, the material thickness also is dependent upon the ratio of the perimeter length of the geometric elements to the area occupied by the geometric elements. Conventional fill techniques do not take into account this perimeter-to-area ratio for the geometric elements, making the selection of the fill density amount to be added to an integrated circuit design unpredictable.
Adding unnecessary fill structures may increase the capacitance of the material layer. If the designer or manufacturer inadvertently fills too much of the empty regions with fill geometric elements, or places fill geometric elements too close to functional geometric elements, the increased capacitance in the manufactured material layer may cause the surrounding circuit devices to exceed their minimum timing requirements. Still further, each additional fill geometric element in a design may increase the time and complexity of optical proximity correction processing or resolution enhancement technology processing of the circuit layout design prior to manufacture.